In many processors, main memory is often much smaller than the amount of data stored on an associated disk. Therefore, there are several regular transaction types that are achieved via access to the disk, such as initialization routines, searching index tables, swapping page tables, error recovery, page replacement, and retrieving data in response to a cache miss. Avoiding these disk accesses, can reduce the power and improve performance of the memory processes in the CPU.
For example a disk data access must go through a complex path having a long latency when a memory miss occurs. Then when critical data is corrupted in the main memory and needs to be recovered, it is typically recovered from disk. Erroneous data recovered from disk to main memory has to go through a complex path that may include a memory channel, interconnect, PCIe buffer, PCH bus, and disk interface wherein any error in this path can shut down the recovery process. Furthermore, if the data to transmit the recovery request to the disk itself is corrupted, recovery may not be possible.
Main memory is typically implemented as standard double data rate (DDR) dual in-line memory modules (DIMMs) or could also be eDRAM or MCDRAM or other conventional DRAM solution. Therefore, in low power situations, or to initialize instant resume from a sleep state, an NVM is desirable to conserve energy otherwise consumed by the volatile memory of DDR DIMMs and to resume from the sleep state without the high latency of accessing the disk. This kind of fast power state transition is essential for the system total power efficiency. This architecture can be extremely useful for future computer system across all segments. However, a large-capacity secondary level of memory has not traditionally been feasible in light of the latency associated with the use of NVM-based memory units.
The cost and latency of non-volatile memory (NVM) was traditionally a deterrent in implementing a large-capacity NVM as a part of a storage system in a computer system. However, improved performance and cost of NVMs, including for example PCM and PCMS type solutions, makes implementing an NVM as part of a memory hierarchy feasible. Accordingly, there is a need in the art for an efficient implementation of large-capacity NVM technologies in a CPU.